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Padmanabhan, T. R. Design through verilog HDL / by T. R. Padmanabhan and B. Bala Tripura Sundari. - New Jersey : IEEE, 2004 xii, 455p. :ill. Includes bibliographical references and index. 0-471-44148-1 Rs.3797.62 * Computer hardware description language Verilog * Sundari, B. Bala Tripura * Title
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