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Design and Optimization of Polygon-shaped-Gate-Oxide TFET for Low Power Applications by Samadrita Bhuiya

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MapLanguage: English Publication details: 2022 Silchar NIT Description: xiii,35p;30cmSubject(s):

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Dissertation note: National Institute of Technology, Silchar Master of Technology 2022

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Holdings
Item type	Current library	Call number	Status	Date due	Barcode
Dissertation	National Institute of Technology, Silchar Central Library@NITS	621.39 BHU (Browse shelf(Opens below))	Available		D1519

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Previous	621.39 BAL Digital logic design principles	621.39 BAL Digital logic design principles	621.39 BAL Digital logic design principles	621.39 BHU Design and Optimization of Polygon-shaped-Gate-Oxide TFET for Low Power Applications	621.39 DAS Hardware implementation of a Support Vector Machine (SVM) Classifier	621.39 DAS Design of an Efficient Two Error Correcting BCH Code Decoder	621.39 DAS Design of a Millimeter-Wave Rectenna for Energy Harvesting	Next

National Institute of Technology, Silchar Master of Technology 2022

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