TY  - BOOK
AU  - Padmanabhan,T.R.
AU  - Tripura Sundari, B.Bala
TI  - Design through verilog HDL
SN  - 9812-53-131-9
U1  - 621.392 
PY  - 2004///
CY  - Singapore
PB  - John Wiley
KW  - Computer hardware description language
KW  - Switch level-Modeling
KW  - Verilog
N1  - Includes bibliographical references and index; Book Emporium
ER  -