TY  - MAP
AU  - Niveditha, M.
AU  -  
TI  - Through-silicon-via (TSV) insertion for area optimization of SoC in foveros technology
U1  - 621.382 
PY  - 2023///
CY  - Silchar
PB  - NIT
KW  - Electronics & Communication Engineering
N1  - Guided by Brinda Bhowmick; National Institute of Technology, Silchar
ER  -