| 000 | 00654nam a2200217Ia 4500 | ||
|---|---|---|---|
| 008 | 160330s9999||||xx |||||||||||||| ||und|| | ||
| 020 |
_a0-471-44148-1 _cRs.3797.62 |
||
| 040 | _aCentral Library-NITS | ||
| 041 | _aEnglish | ||
| 082 | _a621.392 | ||
| 100 | _aPadmanabhan, T. R. | ||
| 245 |
_aDesign through verilog HDL _cby T. R. Padmanabhan and B. Bala Tripura Sundari |
||
| 260 |
_aNew Jersey _bIEEE _c2004 |
||
| 300 | _axii, 455p. :ill. | ||
| 500 | _aIncludes bibliographical references and index. | ||
| 521 | _bOverseas | ||
| 650 | _aComputer hardware description language | ||
| 650 | _aVerilog | ||
| 700 | _aSundari, B. Bala Tripura | ||
| 942 | _cBK | ||
| 999 |
_c10645 _d10645 |
||