| 000 | 00700nam a2200229Ia 4500 | ||
|---|---|---|---|
| 008 | 160330s9999||||xx |||||||||||||| ||und|| | ||
| 020 |
_a9812-53-131-9 _cRs.261.50 |
||
| 040 | _aCentral Library-NITS | ||
| 041 | _aEnglish | ||
| 082 |
_a621.392 _bPAD |
||
| 100 | _aPadmanabhan,T.R. | ||
| 245 |
_aDesign through verilog HDL _cby T.R.Padmanabhan and B.Bala Tripura Sundari |
||
| 260 |
_aSingapore _bJohn Wiley _c2004 |
||
| 300 | _axii, 455p. :ill. | ||
| 500 | _aIncludes bibliographical references and index. | ||
| 521 | _bBook Emporium | ||
| 650 | _aComputer hardware description language | ||
| 650 | _aSwitch level-Modeling | ||
| 650 | _aVerilog | ||
| 700 | _aTripura Sundari, B.Bala | ||
| 942 | _cBK | ||
| 999 |
_c18475 _d18475 |
||