000			00650nem a2200205Ia 4500
005			20230513180041.0
008			160331s9999 xx 000 0 und d
040			_aCentral Library-NITS
041			_aEnglish
082			_a621.39 _bSAU
100			_aSaurav, Kumar
245			_aSDRAM controller core using Wishbone Technology _cby Kumar Sauravxv
260			_c2020 _aSilchar _bNIT
300			_axv,36p;30cm
502			_aNational Institute of Technology, Silchar _bMaster of Technology _d2020
650			_aElectronics and Communication Engineering
650			_aMicroelectronics and VLSI Design
700			_aChakraborty, Ujjal
942			_cDE
999			_c25409 _d25409