| 000 | 00661nem a2200205Ia 4500 | ||
|---|---|---|---|
| 005 | 20231011160715.0 | ||
| 008 | 160331s9999 xx 000 0 und d | ||
| 040 | _aCentral Library-NITS | ||
| 041 | _aEnglish | ||
| 082 |
_a621.382 _bNIV |
||
| 100 | _aNiveditha, M. | ||
| 245 |
_aThrough-silicon-via (TSV) insertion for area optimization of SoC in foveros technology _cby Niveditha, M. |
||
| 260 |
_c2023 _aSilchar _bNIT |
||
| 300 | _aviii, 41p. | ||
| 500 | _aGuided by Brinda Bhowmick | ||
| 502 |
_aNational Institute of Technology, Silchar _bMaster of Technology _d2023 |
||
| 650 | _aElectronics & Communication Engineering | ||
| 700 | _a | ||
| 942 | _cDE | ||
| 999 |
_c27086 _d27086 |
||