621.392 PAD 51531 51530
Padmanabhan,T.R. Design through verilog HDL / by T.R.Padmanabhan and B.Bala Tripura Sundari. - Singapore : John Wiley, 2004 xii, 455p. :ill. Includes bibliographical references and index. 9812-53-131-9 Rs.261.50 * Computer hardware description language Switch level-Modeling Verilog * Tripura Sundari, B.Bala * Title
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