Through-silicon-via (TSV) insertion for area optimization of SoC in foveros technology by Niveditha, M.
Material type: MapLanguage: English Publication details: 2023 Silchar NITDescription: viii, 41pSubject(s): DDC classification:- 621.382 NIV
Item type | Current library | Call number | Status | Date due | Barcode |
---|---|---|---|---|---|
Dissertation | National Institute of Technology, Silchar Central Library@NITS | 621.382 NIV (Browse shelf(Opens below)) | Available | D1838 |
Guided by Brinda Bhowmick
National Institute of Technology, Silchar Master of Technology 2023
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