Routing congestion in VLSI circuits: estimation and optimization by Prashant Saxena, Rupesh S Shelar and Sachin S Sapatnekar

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Material type: Text

TextLanguage: English Publication details: New York Springer 2007Description: xiv, 248p., illISBN:

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Holdings
Item type	Current library	Call number	Status	Date due	Barcode
Books	National Institute of Technology, Silchar	621.395 SAX (Browse shelf(Opens below))	Available		84163

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Previous	621.395 ROY Low-power CMOS VLSI circuit design	621.395 ROY Low-power CMOS VLSI circuit design	621.395 ROY Low-power CMOS VLSI circuit design	621.395 SAX Routing congestion in VLSI circuits: estimation and optimization	621.395 SAX Routing congestion in VLSI circuits: estimation and optimization	621.395 SAX Routing congestion in VLSI circuits: estimation and optimization	621.395 SAX Routing congestion in VLSI circuits: estimation and optimization	Next

Includes index

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